A Defect-Tolerant Mixed-Grain Reconfigurable Multiprocessor Array Master of Science Thesis in Embedded Electronics System Design DANISH

Gothenburg the non-exclusive right to publish the Work electronically and in a non-commercial purpose make it accessible on the Internet. The Author warrants that he/she is the author to the Work, and warrants that the Work does not contain text, pictures or other material that violates copyright law. The Author shall, when transferring the rights of the Work to a third party (for example a publisher or a company), acknowledge the third party about this agreement. If the Author has signed a copyright agreement with a third party regarding the Work, the Author warrants hereby that he/she has obtained any necessary permission from this third party to let Chalmers University of Technology and University of Gothenburg store the Work electronically and make it accessible on the Internet. Abstract Defect tolerance at chip level is currently an evolving field. With continues improvement in transistor feature size and device count the reliability of hardware has became a major concern for manufactures and designers alike. Hence a solution that can address defects at lower level while maintaining a small implementation cost could not only help in keeping the manufacturing cost low but also serves as a base for future reliable yet cost effective devices. The topic of this thesis is related to a similar approach for a RISC processor. We began from previously designed coarse grain implementation of a defect tolerant multiprocessor array and supplement it with a fine-grain " wild-card " like block which could replace any one of the defective pipeline stages in the array when required. Thus would improve the availability of the multiprocessor array at high defect rates. However by doing so the performance of implemented pipeline stages suffers from inherit gate delay of the reconfigurable substrate. Therefore the design has been modified to provide functionality at reasonable performance cost. The proposed design offers graceful degradation and in a worst case scenario exhibits a performance & power overhead of 10X and 1.75X respectively as compare to the baseline processor. With respect to area utilization the proposed fine-grain block requires 2.6X the area of single baseline processor, while in terms of availability the benefit of this approach in a 4 core coarse-grain defect tolerant array becomes apparent at defect rates above 1.3 faults per core.